The present invention relates to systems and methods for design verification of devices. More particularly, the present invention relates to smart instruction generators using network files to produce code for testing processors that may be used in computers or other processing machines.
During development, microprocessors must be exhaustively tested to identify design flaws. Ideally, the processor's performance is verified for all possible circumstances under which it might be operated in the real world. Unfortunately, this would involve testing a potentially infinite number of instruction sequences and therefore require a prohibitively long time to generate and run the test instructions.
To sample a wide range of possible instruction sequences for design verification, random instruction generators were developed. These systems simply generate a random sampling of instructions (typically in the processor's assembly language) which is then converted to machine code and executed on the processor or a logical representation of the processor. In related systems known as pseudo random test generators, the developer weights certain instructions or classes of instructions more heavily than others so that the random instruction are biased toward these desired instructions. These systems allow the developer to stress the microprocessor with certain types of instructions observed to cause difficulties (by weighting those instructions more heavily). For example, if a developer recognizes that instruction sequences having floating point operations identify a particularly high number of bugs, he or she may require that instructions for floating point operations be weighted more heavily. Although random and pseudo-random instruction generators can provide a wide range of possible instructions sequences with minimal user input, they do not intuitively understand which instruction sequences might be most difficult for the microprocessor to handle. Further, for some designs, such instructions may not test an adequately wide spectrum of instruction sequences. Thus, they sometimes fail to adequately test important aspects of a processor's functioning.
In an alternative approach known as a "directed diagnostic," a human programs a sequence of test instructions for verifying the processor design. In so doing, the programmer makes use of his knowledge of real world situations in which the processor might be expected to encounter difficulty. This allows the programmer to design tests which he or she expects to be difficult for the processor to successfully execute. Unfortunately, each user's experience is somewhat limited. Therefore, the test code likely will not sample a sufficiently large number of situations to adequately test the processor. Further, if the programmer was to attempt to write tests encompassing a sufficiently wide range of test cases, he or she would eventually spend a prohibitively long time developing the test code.
Thus, there exists a need for an instruction generator that can provide test instructions covering a wide spectrum of possible processor instruction sequences and can learn which instruction sequences are most likely to stress the microprocessor.